TO
Product introduction
The abbreviation for Transistor Outline Package, Transistor shape package, is a kind of straight plug package.
Product features
Typically, the transistor shape TO is a plug – in package design. In recent years, surface mount market demand increases, TO packaging also has some progress TO surface mount packaging design.
Application
SOT is one of the most mature industry standard packages used in magnetic induction chips, small appliances, motor drives and other products.
Process characteristics
Refer to or meet JEDEC standards
Customized design lead frame design and multi-specification pad size to meet different customer needs
Green manufacturing, lead-free process
Reliability test standard
The test criteria is zero defects in 77 sampling units
JEDEC Prerequisite: J-STD-20/JESD22-A113
Temperature/humidity test: 85ยฐC/85% RH, JEDEC 22-A101
Temperature/humidity test: 85ยฐC/85% RH, JEDEC 22-A101
Temperature cycle test: -65~150 โ, JEDEC22-A104
High temperature storage test: 150ยฐC, JEDEC 22-A103
High acceleration stress test: 130ยฐC/85% rh /33.5 PSIA, JEDEC 22-A110/A118
| ๅบ่ | ๅคๅ | ่ ณๆธ | ๅกๅฐ้ซ้ท (D)mm | ๅกๅฐ้ซๅฏฌ (E)mm | ๅกๅฐ้ซๅ (A2)mm | ็ขๅ็ธฝๅฏฌ (E1)mm | ่
ณ้่ท (e)mm | ่
ณๅฏฌ ( b)mm | ่
ณ้ท ( L)mm | ็ซ้ซ (A1)mm | ๆๅคงๅบๅณถ ๅฐบๅฏธmil | ๆๅคงๅบๅณถ ๅฐบๅฏธum | ๆกๆถๅๅบฆ mm | ๆกๆถ ๆๅ | ้ป่ช ๅ ่ฃๆนๅผ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | TO92-3L | 3L | 4.10ยฑ0.1 | 4.70ยฑ0.1 | 1.57ยฑ0.1 | 1.27 | 0.40-0.57 | 13.00ยฑ0.5 | 129ร92 | 3280ร2340 | 0.38 | 1ร50 | ้้ปๅธถ | ||
| 2 | TO92S | 3L | 4.0ยฑ0.1 | 3.2ยฑ0.1 | 1.55ยฑ0.1 | 1.27 | 0.35-0.56 | 14.5ยฑ0.5 | 62ร82 | 1574ร2091 | 0.38 | 1ร50 | ้้ปๅธถ | ||
| 3 | TO94L | 4L | 5.22ยฑ0.1 | 3.65ยฑ0.1 | 1.56ยฑ0.1 | 1.27 | 0.40-0.57 | 14.5ยฑ0.5 | 152ร81 | 3861ร2065 | 0.38 | 1ร40 | ้้ปๅธถ |
